The present invention relates generally to random access memory (RAM) circuits. More specifically, but without limitation thereto, the present invention relates to a complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) cell in which the SRAM cell transistor threshold voltages are dynamically driven to increase cell speed, reduce cell leakage, and improve cell stability.
In conventional CMOS SRAM cells, the substrate terminal is connected to the source terminal of the MOSFET. The source terminal of a P-channel MOSFET is connected to Vdd, and the source terminal of an N-channel MOSFET is connected to Vss, typically ground (Gnd).
Pull-down and access transistors are typically sized to ensure adequate cell speed and noise margin. Increasing the size of the pull-down transistors lowers their on-resistance, so that the xe2x80x980xe2x80x99 storage node rises by a smaller voltage during read access. The smaller the voltage rise, the higher the noise margin. Similarly, increasing the size of the cell access transistors lowers their on-resistance, so that more current flows from the precharged bit lines through the access transistors and the pull-down transistors. Higher bit line current results in a higher read current and a correspondingly faster cell speed. The MOSFET gate threshold voltage typically must be scaled for each new technology as supply voltages are reduced to maintain the difference between the supply voltage and the gate threshold voltage. The larger the difference between the supply voltage and the gate threshold voltage, the greater the MOSFET current drive and cell speed.
With each new technology generation, the dimensions of source-drain junction depth, lower-level interconnect geometry, gate oxide thickness, and channel length of metal-oxide semiconductor field-effect transistors (MOSFET) are scaled down to increase the density, functionality, and performance of CMOS circuits. Microscopic variations in the number and location of dopant atoms in the channel region induce electrical deviations in device threshold voltage. These intrinsic fluctuations in device threshold voltage at the atomic level are most pronounced in minimum geometry transistors commonly used in area constrained circuits such as SRAM cells. In minimum geometry transistors, the transistor channel width equals the transistor channel length. Narrow width effects, soft error rate, low voltage operation, temperature and process variations, and source-drain junction parasitic resistance all contribute to increasing the instability, i.e., decreasing the static noise margin (SNH), of a conventional six-transistor (6T) SRAM cell. With projected increases in percentage of chip transistors devoted to SRAM cache memory in high performance microprocessors and application-specific integrated circuits (ASICs), sub-threshold leakage currents from an overwhelming number of inactive cells are projected to become larger than the currents from a much smaller number of active circuits switching during a memory access, placing limits on the scaling of threshold voltage of cell transistors. As the number of memory cells increases, the leakage currents become much higher than the switching currents during a memory access. This problem becomes more severe when the gate threshold voltage is scaled down with the supply voltage, because the sub-threshold leakage current increases exponentially. The increase in sub-threshold leakage current with low threshold voltage limits the extent to which MOSFET voltages may be scaled.
The bit line (BL) delay, or cell delay, is determined primarily by bit line capacitance, cell read current, and sensitivity of sense amplifiers. The bit line delay limits SRAM performance because bit line capacitance and sense amplifier sensitivity do not scale proportionally with transistor dimensions. Raising the threshold voltage of cell transistors reduces standby power dissipation from the cell array but imposes a severe penalty on bit line delay by reducing the maximum MOSFET saturation current, thus compromising cell read current and speed of minimum geometry cell transistors.
Several SRAM cell architectures have been proposed to alleviate one or more of the above limitations facing SRAM cell scaling. In these SRAM cell architectures, however, the improvements in cell drive obtainable by driving the word line voltage higher than Vdd, or boosted word line voltage, are offset by the high gate threshold voltage of the cell transistors and corresponding increased bit line delay.
The present invention advantageously addresses the problems above as well as other problems by providing a source pulsed, dynamic threshold complementary metal oxide semiconductor static random access memory that dynamically controls cell transistor threshold voltage to increase cell stability, decrease cell standby power, and reduce cell delay.
In one embodiment, the present invention may be characterized as a memory cell that includes a low storage node and a high storage node wherein the low storage node is driven below Vss during a read access and the high storage node is driven above Vdd during the read access.
In another embodiment, the present invention may be characterized as a memory cell that includes a plurality of N-channel field effect transistors (NFETs) isolated in a P-well and driven by a common word line.
In still another embodiment, the present invention may be characterized as a memory cell that includes a pull-up device that includes a power line terminal for connecting to a pulsed power line driver, a gate terminal connected to a first storage node, and an output terminal connected to a second storage node; and a pull-down device that includes a source line terminal for connecting to a pulsed source line driver, a gate terminal connected to the first storage node, and an output terminal connected to the second storage node.